CMOS design of adaptive fuzzy ASICs using mixed-signal circuits

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level - prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5 /spl mu/m single-poly technology

Multiplexing architecture for mixed-signal CMOS fuzzy controllers

Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the advantages of an analogue implementation, while allowing a marked increment in system complexity, is presented.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

A modular CMOS analog fuzzy controller

The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy chips with optimum speed/power figures. This paper presents a sixteen rules-two inputs analog fuzzy controller in a CMOS 1 /spl mu/m single-poly technology based on building blocks implementations previously proposed by the authors (1995). However, such building blocks are rearranged here to get a highly modular architecture organized from two high level blocks: the label block and the rule block. In addition, sharing of membership function circuits allows a compact design with low area and power consumption and its highly modular architecture will permit to increase the number of inputs and rules in future chips with hardly design effort. The paper includes measurements from a silicon prototype of the controller

Neuro-fuzzy chip to handle complex tasks with analog performance

This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided

A multiplexed mixed-signal fuzzy architecture

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal

A mixed-signal fuzzy controller and its application to soft start of DC motors

Presents a mixed-signal fuzzy controller chip and its application to control of DC motors. The controller is based on a multiplexed architecture presented by the authors (1998), where building blocks are also described. We focus here on showing experimental results from an example implementation of this architecture as well as on illustrating its performance in an application that has been proposed and developed. The presented chip implements 64 rules, much more than the reported pure analog monolithic fuzzy controllers, while preserving most of their advantages. Specifically, the measured input-output delay is around 500 ns for a power consumption of 16 mW and the chip area (without pads) is 2.65 mm/sup 2/. In the presented application, sensed motor speed and current are the controller input, while it determines the proper duty cycle to a PWM control circuit for the DC-DC converter that powers the motor drive. Experimental results of this application are also presented.Comisión Interministerial de Ciencia y Tecnología TIC99-082

A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8

Trabajo final de máster: ser docente de ciencias sociales

Este trabajo constituye la síntesis de los aprendizajes realizados en el Máster de Profesorado en la especialidad de Geografía e Historia. Por lo tanto, se va a centrar en una reflexión íntegra sobre lo que significa ser docente de Ciencias Sociales, a través de los competencias adquiridas en las asignaturas del máster y de la experiencia vivida en el centro educativo

Tactile Sensors Based on Conductive Polymers

This paper presents results from a selection of tactile sensors that have been designed and fabricated. These sensors are based on a common approach that consists in placing a sheet of piezoresistive material on the top of a set of electrodes. We use a thin film of conductive polymer as the piezoresistive mate¬rial. Specifically, a conductive water-based ink of this polymer is deposited by spin coating on a flexible plastic sheet, giving it a smooth, homogeneous and conducting thin film. The main interest in this procedure is that it is cheap and it allows the fabrication of flexible and low cost tactile sensors. In this work we present results from sensors made using two technologies. Firstly, we have used a flexible Printed Circuit Board (PCB) technology to fabricate the set of electrodes and addressing tracks. The result is a simple, flexible tactile sensor. In addition to these sensors on PCB, we have proposed, designed and fabricated sensors with screen printing technology. In this case, the set of electrodes and addressing tracks are made by printing an ink based on silver nanoparticles. The intense characterization provides us insights into the design of these tactile sensors.This work has been partially funded by the spanish government under contract TEC2006-12376-C02

A Large Area Tactile Sensor Patch Based on Commercial Force Sensors

This paper reports the design of a tactile sensor patch to cover large areas of robots and machines that interact with human beings. Many devices have been proposed to meet such a demand. These realizations are mostly custom-built or developed in the lab. The sensor of this paper is implemented with commercial force sensors. This has the benefit of a more foreseeable response of the sensor if its behavior is understood as the aggregation of readings from all the individual force sensors in the array. A few reported large area tactile sensors are also based on commercial sensors. However, the one in this paper is the first of this kind based on the use of polymeric commercial force sensing resistors (FSR) as unit elements of the array or tactels, which results in a robust sensor. The paper discusses design issues related to some necessary modifications of the force sensor, its assembly in an array, and the signal conditioning. The patch has 16 × 9 force sensors mounted on a flexible printed circuit board with a spatial resolution of 18.5 mm. The force range of a tactel is 6 N and its sensitivity is 0.6 V/N. The array is read at a rate of 78 frames per second. Finally, two simple application examples are also carried out with the sensor mounted on the forearm of a rescue robot that communicates with the sensor through a CAN bus